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@pulp-platform

pulp-platform

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  1. Deeploy Deeploy Public

    DNN Compiler for Heterogeneous SoCs

    Python 79 50

  2. carfield carfield Public

    A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

    Tcl 132 37

  3. cheshire cheshire Public

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

    Verilog 376 120

  4. snitch_cluster snitch_cluster Public

    An energy-efficient RISC-V floating-point compute cluster.

    C 152 117

  5. axi axi Public

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog 1.7k 374

  6. ara ara Public

    The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

    C 552 207

Repositories

Showing 10 of 332 repositories
  • gwaihir Public

    aka Lago-Mio

    pulp-platform/gwaihir's past year of commit activity
    C 7 5 9 12 Updated Oct 9, 2026
  • magia-sdk Public
    pulp-platform/magia-sdk's past year of commit activity
    C 7 Apache-2.0 12 9 9 Updated Oct 9, 2026
  • axi_llc Public
    pulp-platform/axi_llc's past year of commit activity
    SystemVerilog 37 28 5 3 Updated Oct 9, 2026
  • ManyRVData Public

    This is the repository for CachePool architecture for the ManyRVData project

    pulp-platform/ManyRVData's past year of commit activity
    C 3 Apache-2.0 7 17 3 Updated Oct 9, 2026
  • chimera-sdk Public
    pulp-platform/chimera-sdk's past year of commit activity
    C 4 11 6 0 Updated Oct 9, 2026
  • MXCore Public
    pulp-platform/MXCore's past year of commit activity
    Python 1 Apache-2.0 2 0 0 Updated Oct 9, 2026
  • cheshire Public

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

    pulp-platform/cheshire's past year of commit activity
    Verilog 376 120 21 33 Updated Oct 9, 2026
  • redundancy_cells Public

    SystemVerilog IPs and Modules for architectural redundancy designs.

    pulp-platform/redundancy_cells's past year of commit activity
    SystemVerilog 23 12 0 7 Updated Oct 9, 2026
  • FlooNoC Public

    A Fast, Low-Overhead On-chip Network

    pulp-platform/FlooNoC's past year of commit activity
    SystemVerilog 358 Apache-2.0 80 23 8 Updated Oct 9, 2026
  • TeraNoC Public

    An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.

    pulp-platform/TeraNoC's past year of commit activity
    C 41 Apache-2.0 12 0 2 Updated Oct 8, 2026